SFMDV=others, SFMDTY=0
Clock Control Register
| SFMDV | Serial interface reference cycle selection (* Pay attention to the irregularity.)NOTE: When PCLKA multiplied by an odd number is selected, the high-level width of the SCK signal is longer than the low-level width by 1 x PCLKA before duty ratio correction. 0 (others): ( SFMDV + 2 ) x PCLKA 16 (10000): 18 x PCLKA 17 (10001): 20 x PCLKA 18 (10010): 22 x PCLKA 19 (10011): 24 x PCLKA 20 (10100): 26 x PCLKA 21 (10101): 28 x PCLKA 22 (10110): 30 x PCLKA 23 (10111): 32 x PCLKA 24 (11000): 34 x PCLKA 25 (11001): 36 x PCLKA 26 (11010): 38 x PCLKA 27 (11011): 40 x PCLKA 28 (11100): 42 x PCLKA 29 (11101): 44 x PCLKA 30 (11110): 46 x PCLKA 31 (11111): 48 x PCLKA |
| SFMDTY | Selection of a duty ratio correction function for the SCK signal 0 (0): Serial interface reference cycle selection (* Pay attention to the irregularity.) 1 (1): Delays the rising of the SCK signal by 0.5PCLKA.( Valid with PCLKA multiplied by an odd number) |